Josef J. Schmid

Patent Applications

  1. Integrated Circuit and Method for Testing, 1998, EP98304773.9
  2. Method for Achieving Scan Testability of an Integrated Circuit Including Multiple Clock Systems, 2000, EP00310084.9
  3. Boundary Scan Delay Chain for Crosschip Delay Measurement, 2001, EP01301472.5
  4. Delayed Flash Clear Scan Flip-Flop To Be Implemented in Complex Integrated Circuit Designs, 2001, EP01306895.2
  5. Functional-Concurrent Power, Current and Temperature Characterization of Complex ASIC/SOCs by "Underfloor Heating" with Special Frequency-Controlled Scan-FFs, 2002 (onhold)
  6. Aggressor Blocking Clock-Multiplexer, 2002  (onhold)
  7. Local Scan Switch Methodology for DFT of Complex SOC Designs, 2002 (onhold)
  8. Special Ringoscilator (ROSC) Implementation for Aging & Wearout Analysis, 2017 (onhold)
  9. Verfahren und Vorrichtung zur Bestimmung einer Kenngröße für elektronische Bauteile, 2021, DE102021208363A1 (ROSC-IP)
  10. Verfahren zum Testen eines Messsystems sowie Testsystem, 2021, DE102021203365A1 (DelayLines/LiDAR)

Status: 2022