J. Schmid, Untersuchungen an aktiven Filtern mit geschalteten
Kapazitäten, Diplomarbeit, Fachhochschule Regensburg, 1981
A. Lamm, N. Michel und J. Schmid, Zweidraht-Kennzeichenumsetzer mit
hochintegrierten Schaltkreisen für den Einsatz in digitalen
Vermittlungsanlagen, PKI Technische Mitteilungen, 1984
F. Welten, A. Delaruelle, F. van Wyk, J. van Meerbergen, J. Schmid and
K. Rinner, A 2 Micron CMOS, 10 MHz, Microprogrammable Vector Processing
Unit With an ON-Chip 3-port Registerfile for Incorporation in Single
Chip General Purpose Digital Signal Processors, VLSI Signal
Processing, IEEE Press 1984
F. Welten, A. Delaruelle, F. van Wijk, J. van Meerbergen, J. Schmid,
K. Rinner, K. van Eerdewijk and J. Wittek, A 2-um CMOS 10-MHz
Microprogrammable Signal Processing Core With an ON-Chip Multiport
Memory Bank, IEEE Journal of Solid-State Circuits, Vol SC-20, NO. 3,
June 1985
F. van Wijk, J. van Meerbergen, F. Welten, J. Stoter, J. Huisken, A.
Delaruelle, K. van Eerdewijk, J. Schmid and J. Wittek, A 2-um CMOS 8-MHz
Digital Signal Processor with Parallel Processing Capability, IEEE
Journal of Solid-State Circuits, Vol SC-21, NO. 5, October 1986
J. van Meerbergen, F. Welten, F. van Wijk, J. Stoter, J. Huisken, A.
Delaruelle, K. van Eerdewijk, J. Schmid, J. Wittek,
An 8MIPS CMOS digital signal processor, IEEE Solid-State Circuits
Conference, Digest of Technical Papers, Volume XXIX, Feb 1986
F. van Wijk, F. Welten, J. van Meerbergen, J. Stoter, J. Huisken, A.
Delaruelle, K. van Eerdewijk, J. Schmid and J. Wittek, On the IC
Architecture and Design of a 2-um CMOS 8 MIPS Digital Signal Processor
with Parallel Processing Capability: The PCB5010/5011, IEEE Proceedings
ICASSP, Tokyo 1986
K. Hellwig, K. Rinner, J. Schmid und P. Vary, Digitaler
Signalprozessor für den Sprach- und Audiofrequenzbereich, PKI Technische
Mitteilungen, 1/1986
H. Ebert, J. Schmid und J. Schuck, Neue Syntheseverfahren zur
Entwurfsautomatisierung von ASIC-Bausteinen, PKI Technische
Mitteilungen, 2/1989
T. Frey, J. Knäblein, D. Markuske, and J. Schmid. Integrations- und
Testkonzept eines CMOS ASICs mit komplexen RAM-Strukturen. In
Tagungsband SMT/ES&S/Hybrid, Nuremberg 1995
J. Schmid and J. Knäblein, STMCS - Scan Technique for Multi Clock
Systems. In Proceedings 15th Lucent Conference of Electronic Testing
LCET98, Princeton, NJ, USA, 1998
J. Knäblein and J. Schmid, STMCS - Scan Technique for Multi Clock
Systems, Lucent Design User Conference LTDUC98 - Holmdel, NJ, USA, 1998
S. Roy, J. Knäblein and J. Schmid, Multiple Clocks in Scan-Based BIST,
In Proceedings 16th Lucent Conference of Electronic Testing
LCET99, Princeton, NJ, USA, 1999
R. Alblas, S. Bhawmik, F. Crane, G. Frazer, K. Honea, A. Kandalaft, J.
Kane, E. Kramer, M. Mastenbrook, R. Miu, P. Murphy, B. Nützel , J.
Nyquist, R. Pflaum, J. Schmid, R. Srinivasan, V. Thamm, C. Wilde, S. Wu
and C. Zimmerman, ASIC Design- for- Testability Guide, In Proceedings
16th Lucent Conference of Electronic Testing LCET99, Princeton,
NJ, USA, 1999
J. Schmid and J. Knäblein, Advanced Synchronous Scan Test Methodology
for Multi Clock Domain ASICs. In IEEE Proceedings VLSI Test
Symposium VTS99, Dana Point, CA, USA, 1999
J. Knäblein, R. Willecke and J. Schmid, Using TetraMAX ATPG for
Multi-Clock-Systems, Synopsys SNUG00, Paris, France, 2000
J. Schmid, T. Schüring and C. Smalla, BSDC - Cross-Chip Delay
Measurement Using the Boundary Scan Delay Chain, Lucent Conference
DFX00, Naperville, IL, USA, 2000
T. Schüring, J. Schmid and C. Smalla, BSDC - Cross-Chip Delay
Measurement Using the Boundary Scan Delay Chain, Lucent Design User
Conference LTDUC00, Holmdel, NJ, USA, 2000
C. Smalla, J. Schmid, and T. Schüring, Using the Boundary Scan Delay
Chain for Cross-Chip Delay Measurement and Characterization of Delay
Modelling Flow, In IEEE Proceedings International Symposium on Quality
of Electronic Design ISQED01, San
Jose, CA, USA, 2001
J. Schmid, M. Felkl, P. Munninger, C. Rauch, H. Uhl, L. Thomas, S.
Vlachodiamantis, D. Govindaraj, H. Rauch, A VHDL Design & Test
Methodology for a Radiation Hardened Diagnosis Device, 22. Workshop
"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" TuZ
2010, Paderborn, Germany
Z. Cai, N. Franchi, J. Schmid, H. Rauch, R. Weigel, A new IP core
integration concept for signal manipulation and timing adjustment using
a configurable I/O architecture, 23. GI/GMM/ITG Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen (TUZ
2011), Passau (Germany)
J. Schmid, Echtzeit-Diagnose von redundanten Systemen und
Alterungseffekten im medizinischen Strahlenumfeld, Innovation Forum
Embedded Systems (BICCnet 2011),
München
H. Li , J. Schmid, H. Rauch, An Advanced IP Core for Robust Digital
Design and Aging Monitoring in critical radiation environments, Electrical
and Electronic Engineering for Communication (EEEfCOM
2011), Ulm (Germany)
J. Schmid, H. Li, P.
Munninger, G. Schmidt, H.
Rauch,An
Advanced VHDL/IP-Core for Embedded Aging Monitoring of Analog and
Mixed Signal Applications in Sensitive Radiation Environments, Analog2011,
Erlangen (Germany)
J. Schmid, B. von Edlinger, A. Plange, F. Lehmann, Automotive
System Verification using Saber/Modelsim Cosimulation in Conjunction
with ISO 26262, SNUG-2012,
Munich
J. Schmid, H. Rauch, Ein wiederverwendbarer VHDL / IP-Core zur
Überwachung der Alterung von sensitiven mikroelektronischen Schaltungen,
25. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen (TUZ
2013), Dresden (Germany)
A. Plange, E. Kyrlies-Chrysoulidis, J. Schmid, T. Gürtler,
HW/SW-Cosimulation of ASICs and SW Drivers for Fault Analysis and
Regression Tests, CSC-2013
(Continental SW Conference, confidential), Timisoara, Romania
J. Schmid, M. Eckl, M. Arabackyj, A. Plange, On/Offline Fault
Insertion & Analysis in a Virtual ASIC System Simulation
Environment, 26. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen (TUZ
2014), Kloster Banz (Germany)
E. Kyrlies-Chrysoulidis, T. Guertler, A. Plange, M. Auerswald, J.
Schmid, Hardware/Software Co-Simulation of SPI Enabled ASICs and
Software Drivers for Fault Injection and Regression Tests, DVCON-Europe-2014, Munich
J. Schmid, D. Heinrich, Real Number Modelling and special Ring Oscillator implementation for detection of TID effects in CMOS FPGA Technologies, FPGA-Kongress-2017, Munich
J. Schmid, K. Trenkel, Modelling of Aging Effects and Implementation of IP-Cores for Wear-Out-Detection of FPGAs, FPGA-Kongress-2019, Munich
J. Schmid, K. Trenkel, FPGA-based Modelling of Aging Effects and Implementation of IP-Cores for Wear-Out-Detection,
Embedded World Conference 2020, Nuremberg
J. Schmid, V. Paramesh, FPGA-based Modelling, IP-Implementation and Measurements of Aging Effects due to TID or Electrical and Thermal Stress,
embedded world Conference 2021 DIGITAL, Nuremberg
J. Schmid, M. Frommberger, Asymmetrical Degradation and hidden Duty Cycle Distortion of p/n-MOS Transistors due to TID,
monitored by a special ROSC Implementation,
WhitePaper iSyst GmbH, Nuremberg, 2021